Reg

Reg defines a hardware register used to hold a scalar value. The default reset value for a Reg is the numeric zero value for it’s specified type.

ArgIn, ArgOut, and HostIO are specialized forms of Reg which are used to transfer scalar values to and from the accelerator. ArgIns and ArgOuts are used for setup values at the initialization of the FPGA. ArgIns may not be written to, while ArgOuts generally should not be read from. HostIOs are for values which may be continuously changed or read by the host during FPGA execution.

In Spatial, ArgIns, ArgOuts, and HostIO registers are specified outside the Accel block, in host code.

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Static methods

object Reg
def apply[T:Type:Bits]: Reg[T] Creates a register of type T with a reset value of zero.
def apply[T:Type:Bits](reset: T): Reg[T] Creates a register of type T with the given reset value.

object ArgIn
def apply[T:Type:Bits]: Reg[T] Creates an input argument register of type T with a reset value of zero.

object ArgOut
def apply[T:Type:Bits]: Reg[T] Creates an output argument register of type T with a reset value of zero.

object HostIO
def apply[T:Type:Bits]: Reg[T] Creates a host I/O register of type T with a reset value of zero.

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Infix methods

class Reg[T]
def value: T Returns the value currently held by this register.
def :=(data: T): Unit Writes the given data to this register.
def reset: Unit Resets the value of this register back to its reset value.
def reset(cond: Bit): Unit Conditionally resets the value of this register back to its reset value if cond is true.

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Implicit methods

def readReg[T](reg: Reg[T]): T Implicitly reads the value of this register.